ASIP and accelerators find their raison d’être in performance and power constraints. Many multimedia tasks, such as video decoding or encoding, image processing, or speech recognition, involve heavy computation. If they were performed by a generic purpose processor, such as the ubiquitous ARM processor family, they would require several GHz of clock speed to be carried out in normal speed. This is not reasonable in the mobile world where power consumption needs to be as low as possible (otherwise, your device would get too hot for your hands, or its battery would be sucked empty very quickly).
Besides, ARM architectures are not designed to go to such high frequency. The fastest clocks fall in the range of 1GHz.
Therefore, designers have to resort to purpose designed accelerators; that can perform such tasks at relatively low clock counts (typically between 200 to 400MHz), with a low power consumption. The good match between the task at hand, and the gates dedicated to perform it, allows achieving a good efficiency in terms of silicon surface/MHz/achieved performance.
This is what the mobile and generally speaking, the embedded world, revolves around, contrary to the PC world where area, power and to some lesser extent, cost, are not so important as of today.